Performance Evaluation of Precise/Approximate Multipliers for Filter Applications

Approximate computing techniques are studied to reduce power consumption and area in digital circuits by allowing slight inaccuracies that are acceptable in human perception-focused applications, such as Digital Signal Processing (DSP). This paper presents a novel design for low-power, high-speed approximate circuits, targeting digital signal processing (DSP) applications, particularly in Finite Impulse Response (FIR) filters. Three types of approximate adders, Vedic multipliers and Ripple Carry Adders (RCAs) are proposed, optimized, and analyzed in various bit-length configurations. Reduction in area by 51 %, Power Consumption by 61 % and delay by 85 % is observed in proposed approximate Vedic multiplier compared to normal Vedic multiplier. The proposed approximate FIR filter, designed using these adders and multipliers, achieves notable reductions in area by 52%, power by 42%, and delay by 59% compared to traditional designs, while maintaining comparable frequency response characteristics. Simulation results are evaluated using a 45nm technology file with the help of cadence tool (Cadence Encounter® RTL Compiler v12.10-s012_1).