Systematic Study of Nickel Silicide Based on Wafer-Scale Electrical Testing in 12-in 55 nm CMOS Technology

Nickel silicide quality can greatly influence the CMOS devices and hence chip performances, especially for the technology with smaller nodes. As chips nowadays are normally composed of a huge number of devices, the influence is difficult to be detected by studying a few individual devices due to the probability of defect formation. Thus, wafer-scale investigation is necessary to obtain the overall impact of defect formation, which is however rarely reported. Here, the effect of various fabrication processes on the quality of Ni silicide is investigated systematically by electrical wafer mapping tests of SRAM arrays on 12-in wafers produced by 55 nm CMOS technology that are highly sensitive to defects. It is found that the Siconi (Trademark) precleaning and the 2nd stage rapid thermal annealing (RTA) have a large process window; while the thin thickness of Ni–Pt film and/or the high temperature of 1st stage RTA can greatly promote the Ni encroachment defect formation, which is due to the excess thermal budget that enhances the diffusion of Ni to the Si defects. With the optimization of silicidation process, the formation of Ni encroachment can be effectively suppressed, and the leakage current of SRAM arrays with low (mean value of 7.97 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>4</roman></sup> pA) and uniform distribution (standard deviation of 8.58 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>3</roman></sup> pA) is obtained, and 1M SRAM yield is largely increased to 97.18%, which is outstanding even among the industry technology. This systematic study can provide valuable insight into the defect formation on industrial wafer scale, which can guide the development of high-performance Ohmic contact for CMOS technology with small nodes.