LOW-LATENCY FPGA-BASED ALARM CLOCK SYSTEM ON BASYS 3 WITH REAL-TIME TIMEKEEPING AND BUZZER INTERFACE

This paper presents the design and implementation of a real-time digital alarm clock system on the Xilinx Basys 3 FPGA using Verilog HDL.Unlike traditional microcontroller-based designs, our FPGA-based system leverages hardware-level parallelism for enhanced timekeeping accuracy and responsiveness.The design includes time counting, alarm setting via onboard switches, and real-time display through a four-digit seven-segment display.When the current time matches the preset alarm, a piezo buzzer connected via the Pmod interface is triggered.

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Publication Details

Published
2025-04-16
DOI
https://doi.org/10.34218/ijvd_02_01_001
Primary Topic
Embedded Systems and FPGA Design
Type
article
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article

LOW-LATENCY FPGA-BASED ALARM CLOCK SYSTEM ON BASYS 3 WITH REAL-TIME TIMEKEEPING AND BUZZER INTERFACE

Tejeswara Rao P, Dinesh Kumar, B. Satish Chandra, Sudheer Reddy
Embedded Systems and FPGA Design
article

LOW-LATENCY FPGA-BASED ALARM CLOCK SYSTEM ON BASYS 3 WITH REAL-TIME TIMEKEEPING AND BUZZER INTERFACE

Tejeswara Rao P, Dinesh Kumar, B. Satish Chandra, Sudheer Reddy
article en

Abstract

This paper presents the design and implementation of a real-time digital alarm clock system on the Xilinx Basys 3 FPGA using Verilog HDL.Unlike traditional microcontroller-based designs, our FPGA-based system leverages hardware-level parallelism for enhanced timekeeping accuracy and responsiveness.The design includes time counting, alarm setting via onboard switches, and real-time display through a four-digit seven-segment display.When the current time matches the preset alarm, a piezo buzzer connected via the Pmod interface is triggered.

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LOW-LATENCY FPGA-BASED ALARM CLOCK SYSTEM ON BASYS 3 WITH REAL-TIME TIMEKEEPING AND BUZZER INTERFACE — Tejeswara Rao P, Dinesh Kumar, et al. · (2025) | TGRS Research Map | TGRS