A Combined Strategy for Testing RRAMs After Manufacturing and During Lifetime

The use of Resistive Random Access Memories (RRAMs) for implementing emerging applications depends not only on being able to properly test them after manufacturing but also on being able to guarantee their reliability during their lifetime. These novel non-volatile memories can be affected by manufacturing deviations, process variations and defects, as well as by time-dependent deviations, environmental and temporal variations. In more detail, RRAM's lifetime can be significantly reduced due to in-field degradation, since RRAM cell's endurance can be affected by different parameters, such as temperature and switching speed. In this context, this paper introduces the idea of modifying a Design-for-Testability (DfT) strategy proposed to perform manufacturing testing to also perform online testing aiming the identification of aged RRAM cells during lifetime. The proposed strategy requires the introduction of a DfT_Aging_Circuitry, based on a DfT_Circuitry proposed to perform manufacturing testing only, for identifying faulty-free RRAM cells. The combined strategy was validated using a case study composed of a 4×4 words RRAM block implemented using 28 nm TSMC technology library. Experimental results demonstrated the proposed strategy's detection capability. In more detail, these results show that the DfT_Aging_Circuitry is able to indicate not only when the RRAM cells do not reach the expected resistance values for each resistive state at time zero, but also when the RRAM cells are aged.