Case Study: NASCERR: In-Mission Self-Tuning Error Correction Approach for Space Applications

Nanosatellites have emerged as a viable alternative for space missions due to their adaptability, cost-effectiveness, and potential for data collection operations in Low Earth Orbit (LEO). However, high radiation exposure in LEO poses a significant risk, particularly to the reliability of embedded systems that are vulnerable to memory failures and critical data errors. This context creates the opportunity to develop solutions that ensure the integrity of data stored in memory, which is crucial for mission success and satellite reliability. To address these challenges, this paper presents a new, robust approach for error correction code (ECC) for memory systems used in space applications. The approach, namely NASCERR, is the result of a partnership between Brazilian public universities and the private sector, and aims to validate the ROBC (Robust On-Board Computer), an on-board fault-tolerant computer system for CubeSats. The approach was implemented in a SmartFusion2 M2S025 FPGA operating as an intermediary block (Man-in-the-Middle) between the processor and the SRAM memory system of the satellite. The approach is said to be self-tuning, by adjusting the error correction strategy transparently and on-the-fly, according to the type and frequency of errors detected in memory, in mission mode. Intensive simulation campaigns demonstrated the proposed approach presents high resilience, achieving 100% recovery rate in bit-flip occurrency, while guaranteeing high workload computational performance.