Device Parameter Variation for Gate Engineered Silicon Nanowire (SiNW) MOSFET

This paper examines improved MOSFET performances, such as drain-induced barrier lowering (DIBL), velocity saturation using nanowire technologies to better parameters such as on-current, total current density, tunneling rates, and doping profiles. It studies the traits of nanowire technology as compared to other materials based on TCAD simulation to understand their effectiveness in solving all the issues of conventional MOSFETs. The result shows that Silicon Nanowire has the excellent performance as compared to all the others with an on-current (Id) of 10-5. Thus, on these aspects, SiNWs are kept under regard for next-generation device applications that can excel in terms of electrostatic control, carrier mobility, and scalability. These factors make them a promising candidate for advanced device applications. It also studies net doping and tunneling rates through intensive cut-line studies.