Robust DLBIST for Delay Fault Testing: Minimizing PVT Variability with Zero Temperature Coefficient (ZTC) Voltage

Safety-critical automotive systems require on-chip testing methods to ensure high fault coverage and reliable operation. Periodic Deterministic Logic Built-In Self-Test (DL-BIST) is often used to meet these demands. For automotive applications, DLBIST must operate reliably despite temperature variations, including those caused by ambient changes and self-heating in FinFET and Gate-All-Around (GAA) transistors. Managing these temperature effects typically requires a large volume of test patterns, which can make DLBIST impractical. Advanced transistors like FinFET and GAA exhibit Temperature Effect Inversion (TEI), where the circuit speed increases with temperature at certain supply voltages, although TEI disappears at higher voltages. Research has shown that at a specific optimal voltage, called the Zero Temperature Coefficient (ZTC) voltage, temperature-induced variability is minimized. This paper proposes a robust DLBIST scheme which applies multiple voltages during power-on and power-off tests and the optimal voltage during periodic tests in system operation. Simulations show that generating tests at the ZTC voltage achieves higher fault coverage for Small Delay Faults while significantly reducing the Test Application Time (TAT) at this voltage. This makes periodic DLBIST a feasible solution for in-field self-testing.