Low-Power Linear Feedback Shift Register Using TSPC Flip-Flop and Clock Gating

This paper introduces a novel approach for enhancing the power efficiency of Linear Feedback Shift Registers (LFSRs) through the integration of True Single Phase Clock (TSPC) flip-flops and clock gating techniques. By leveraging TSPC flip-flops and strategically applying clock gating, significant reductions in power consumption are achieved without compromising the functionality or performance of the LFSRs. Compared to other gated clock strategies, power savings are achieved through efficient logic gate implementation and the strategic reduction of XOR gates within the feedback network. The study used transistor-level simulations at standard cells in a 45nm Technology of virtuoso(Cadence). The simulation outcomes demonstrate a significant power reduction when compared to the conventional method.