FS-GDI Technology-Based High-Performance Adder using CNTFETs

A superior functionality adder is one among the vital parts in the design of ASIC. Addition is an essential mathematical method and functions as a fundamental component that assembles all other procedures. As a result, it enables circuit designers to continue developing new models with enhanced features comprising versatility, productivity, endurance, and affordability. In the emerging invention, the Carbon Nanotube FET (CNTFET) is used in place of CMOS innovation for designing circuits. Whereby fully operational basic logic gates are used in the design of a superior functionality adder. By employing 32nm CNTFET Based FS-GDI Technology, the threshold voltage issue that frequently arises in Gate Diffusion Input (GDI) logic is resolved. The major objective of which is to give fast speed and low power consumption with complete voltage swing. Through HSPICE simulations utilizing 32 nm technology models, A comparison is made between the effectiveness of the proposed designs and different entire adder concepts, including CMOS, CPL, hybrid, and GDI. Discovered that the power-delay product (PDP), delay, power dissipation of current full adder cells had all improved.