Literature Review on SRAM Cells Under Stability, Energy, and Power Constraints

The rise of portable devices in our everyday lives has made power optimization a critical focus in contemporary VLSI technology. In recent years, static random-access memory (SRAM) has gained popularity due to its superior performance in VLSI design processes that operate at the submicron or nanoscale. Numerous SRAM cells have been developed to work effectively at lower voltages and with minimized latency. This paper introduces a newly proposed 8T SRAM cell design that offers enhanced read stability when compared to 6T SRAM cells. To tackle the issue of power leakage, two PMOS transistors are incorporated into both the read and write circuits. The proposed 8T SRAM cell demonstrates a marked reduction in leakage current relative to 6T SRAM cells. SRAM serves as the primary memory for small cache-less embedded processors, leading to the development of memories that utilize an SRAM cell optimized for various process parameters, such as energy, stability, and power limitations.