Scalable Convolutional Neural Network Inference on-the-Edge using Low-Density FPGAs

Machine learning (ML) inference-based applications are often considered to be computationally expensive and power exhaustive, restricting useful deployment in low-power use cases. To take advantage of ML in power-constrained edge environments, it is critical to reduce the power consumption and increase the overall efficiency, while aiming for performance acceleration.We present a characteristics study of a low-powered implementation of ML inference focused on-the-edge, aiming for increased efficiency and predictive cost estimation. A scalable inference accelerator architecture for Convolutional Neural Networks (CNNs) consisting of simple functional blocks was developed at Register-transfer Level (RTL) using Verilog® Hardware Description Language (HDL), and was verified at RTL-level verification using RTL testbenches. The integrated system went through functional verification against a predefined golden model, while being optimized for precision and logic utilization.The accelerator was then converted into a fully-parameterized Reconfigurable FPGA IP with additional purpose-built custom debugging glue logic; and validated on FPGA hardware. The system showed a minimum of 740 times acceleration factor during recorded performance evaluations.