A Configurable 2D-Integer DCT Hardware Accelerator Compatible with H.266 Standard based on RISC-V Architecture

This paper presents a system architecture for video compression, including a configurable 2D Discrete Cosine Transform (DCT) hardware accelerator, a CPU, and Direct Memory Access (DMA), implemented on a System on Programmable Chip (SoPC) using the DE10 Pro FPGA. The proposed DCT accelerator utilizes matrix decomposition and replaces traditional multiplications with additions and bit-shifting, enabling an efficient hardware implementation. It supports both square and non-square block sizes, providing flexibility and compatibility with the H.266/VVC standard. The system integrates a NIOS-V CPU based on RISC-V architecture, memory, and DMA to ensure efficient data transfer from video compression pipeline stages like Motion Estimation and Intra/Inter Prediction. Compared to existing solutions, this design overcomes limitations in throughput and block size flexibility, achieving 11,482 Mpixels/s for 64×64 blocks on the DE10 Pro board, supporting 16K video at 60fps. Experimental results also show a throughput of 1,918 Mpixels/s for 32×32 blocks on Virtex 7, supporting 8K video at 50fps, outperforming similar designs in throughput and scalability.