HUNBN, a 16-nm Digital In-Memory-Compute SoC for Edge CNN Application Achieving 24 TOPs/W (4b) at System Level

This work presents HUNBN, a fully digital in-memory-compute (DIMC) system-on-chip (SoC) implemented using 16-nm FinFET CMOS technology. Designed for edge convolution neural network (CNN) applications, the DIMC-based architecture enhances energy efficiency by significantly reducing the energy associated with static random access memory (SRAM). At the macro level, three key techniques are employed to optimize energy and area efficiency: 1) the adoption of a foundry-pushed rule 6T bit-cell array; 2) a split MAC workflow; and 3) synchronous DIMC operation. At the system level, the data movement is tailored to efficiently support both CNN and transposed CNN layers. The proposed design achieves 126 TOPS/W (4-bit MAC) at the macro level and 24 TOPS/W at the system level, while offering a memory density of 508 kB/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a compute density of 1.27 K MAC units/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. This enables a highly energy-efficient, scalable platform for edge CNN applications.