Analytical and Optimal Strategy of Dynamic Current Balancing for Paralleled SiC MOSFETs With Cu-Clip Interconnection Considering Mutual Coupled Inductances

To enhance the electrical performance and reliability of SiC power modules, the study explores Cu-clip as a promising alternative to traditional Al-wire interconnections. SiC power modules, particularly in parallel configurations, encounter challenges in optimizing dynamic current-sharing performance, which limits their maximum current capacity and reliability during switching events. This study proposes an innovative layout design for SiC MOSFET modules, utilizing a coupled parasitic inductance network model to capture better the impact of mutual inductances on dynamic current imbalance. The model derives an equation for equivalent source inductances, accounting for both self-inductance and mutual inductance, providing a foundation for optimizing the layout to minimize dynamic current imbalance. Based on this model, a new Cu-clip structure is designed along with a mathematical analysis aimed at reducing disparities in equivalent source inductances, thereby enhancing dynamic current balancing. The distance between the dies is also increased to mitigate thermal coupling effects. Double pulse tests and simulations were performed to validate the dynamic current balancing performance of the fabricated power module. The results show a 40% reduction in dynamic current imbalance for the optimized layout (Layout B) compared to the baseline configuration (Layout A). This work presents a comprehensive solution to improve the dynamic current performance of paralleled SiC MOSFET power modules, offering significant contributions to the design of more efficient and reliable power electronics.