A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier With Ground Precharge and Charge Transfer Pre Sensing for Sub-1V DRAM

This letter presents a single-ended offsetcompensating (SEOC) with ground precharge bit-line sense amplifier (BLSA). It uses a ground (GND) precharge (PRE) configuration to overcome its limited headroom margin. The single-ended topology that exploits a charge-transfer amplification can eliminate a redundant edge blocks and additional reference circuitry for GND PRE, while maintaining energy efficiency. It is fabricated in a 25-nm DRAM process and compared with offsetcompensation sense amplifier (OCSA). The proposed BLSA can achieve 98% decrease in fail bit count (FBC) compared to OCSA at 0.8V supply voltage and achieve less than 1% performance degradation without redundant edge blocks.

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Publication Details

Journal
IEEE Solid-State Circuits Letters
Published
2025-01-01
DOI
https://doi.org/10.1109/lssc.2025.3561280
Citations
1
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
0.73
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article

A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier With Ground Precharge and Charge Transfer Pre Sensing for Sub-1V DRAM

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Advancements in Semiconductor Devices and Circuit Design
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article

A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier With Ground Precharge and Charge Transfer Pre Sensing for Sub-1V DRAM

Seryeong Yoon, Kyuchang Kang, Jungdon Ihm, Donggeon Kim, Hyunchul Yoon, Y.S. Park, K. S. Cho, Young-Hun Seo, Changsik Yoo, Jae‐Hyuk Kim, Sangjun Hwang, Jae-Joon Song, Incheol Nam, Junhwa Song, C. Lee, Bok-Yeon Won, Injae Bae
article en
1 citations

Abstract

This letter presents a single-ended offsetcompensating (SEOC) with ground precharge bit-line sense amplifier (BLSA). It uses a ground (GND) precharge (PRE) configuration to overcome its limited headroom margin. The single-ended topology that exploits a charge-transfer amplification can eliminate a redundant edge blocks and additional reference circuitry for GND PRE, while maintaining energy efficiency. It is fabricated in a 25-nm DRAM process and compared with offsetcompensation sense amplifier (OCSA). The proposed BLSA can achieve 98% decrease in fail bit count (FBC) compared to OCSA at 0.8V supply voltage and achieve less than 1% performance degradation without redundant edge blocks.

IEEE Solid-State Circuits LettersVol. 8
Samsung (South Korea) (KR)
Affordable and clean energy
Openalex Percentile: Top 30%
Advancements in Semiconductor Devices and Circuit Design
0.73
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