A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier With Ground Precharge and Charge Transfer Pre Sensing for Sub-1V DRAM
This letter presents a single-ended offsetcompensating (SEOC) with ground precharge bit-line sense amplifier (BLSA). It uses a ground (GND) precharge (PRE) configuration to overcome its limited headroom margin. The single-ended topology that exploits a charge-transfer amplification can eliminate a redundant edge blocks and additional reference circuitry for GND PRE, while maintaining energy efficiency. It is fabricated in a 25-nm DRAM process and compared with offsetcompensation sense amplifier (OCSA). The proposed BLSA can achieve 98% decrease in fail bit count (FBC) compared to OCSA at 0.8V supply voltage and achieve less than 1% performance degradation without redundant edge blocks.
Authors
- Seryeong Yoon
- Kyuchang Kang (ORCID: https://orcid.org/0000-0001-7663-9490)
- Jungdon Ihm
- Donggeon Kim (ORCID: https://orcid.org/0000-0003-3430-075X)
- Hyunchul Yoon (ORCID: https://orcid.org/0000-0002-2564-7041)
- Y.S. Park (ORCID: https://orcid.org/0000-0001-8815-2962)
- K. S. Cho
- Young-Hun Seo (ORCID: https://orcid.org/0000-0003-3079-0843)
- Changsik Yoo (ORCID: https://orcid.org/0000-0001-7945-5400)
- Jae‐Hyuk Kim (ORCID: https://orcid.org/0000-0002-3215-2178)
- Sangjun Hwang (ORCID: https://orcid.org/0009-0009-1323-9647)
- Jae-Joon Song
- Incheol Nam
- Junhwa Song
- C. Lee
- Bok-Yeon Won
- Injae Bae
Institutions
- Samsung (South Korea) (KR)
Publication Details
- Journal
- IEEE Solid-State Circuits Letters
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1109/lssc.2025.3561280
- Citations
- 1
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.73