A DC-51.5 GHz Digital Step Attenuator With Sub-5 dB Insertion Loss and 3.1° RMS Phase Error

This article presents an ultrawideband and low-loss digital step attenuator (DSA) with a 15.5-/0.5-dB attenuation range/step. To reduce the insertion loss (IL), a merged attenuation cell is proposed to realize 4-/8-/12-dB attenuation. Moreover, a bridge capacitor is adopted in the merged attenuation cell to expand the bandwidth of the proposed DSA while reducing the phase error between different attenuation states. The proposed DSA is fabricated with a 65-nm bulk CMOS process with a compact core area of only 0.026 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. With measurements, over the entire operating bandwidth from dc to 51.5 GHz, it achieves an IL of less than 5 dB and root-mean-square (rms) attenuation/phase errors of less than 0.25 dB/3.1°, respectively.