An Implementation of Multiplier-Accumulator Unit Using Vedic Multiplier and Reversible Gates

Abstract: The Multiplier-Accumulator Unit (MAC) is a fundamental component in digital signal processing (DSP) and various high-performance computing applications. This paper presents an efficient implementation of a MAC unit using a Vedic multiplier and reversible logic gates to optimize speed, power, and area. The Vedic multiplier, based on ancient Indian mathematics, significantly enhances multiplication efficiency by reducing the number of partial products and carry propagation delays. Additionally, reversible logic gates are employed to minimize power dissipation by reducing information loss, making the design more energy-efficient compared to conventional approaches. The proposed MAC unit architecture is simulated and synthesized using hardware description languages, demonstrating superior performance in terms of speed and power consumption. The results indicate that integrating Vedic multiplication with reversible logic offers a promising solution for lowpower, high-speed arithmetic units in modern computing systems