COPAR: Coordinated Packet Rerouting Attacks in NoC

In modern System-on-Chips (SoCs), the reliance on third - party intellectual property (IP) to meet demanding time-to-market and cost constraints introduces significant security vulnerabilities, particularly through the insertion of Hardware Trojans (HTs). These malicious circuits can severely compromise the performance and reliability of Tiled Chip Multicore Processors (TCMPs), which utilize Network-on-Chip (NoC) architectures for efficient inter-core communication. This paper presents a coordinated HT model that coordinates a packet rerouting attack within an 8×8 mesh NoC. By embedding HTs within the input units of multiple routers, the attack dynamically alters the destination addresses of packets, causing them to take unnecessary and indirect routes through the network. This malicious rerouting results in significant delays, leading to increased average packet latency, reduced instructions per cycle (IPC), and decreased overall throughput. Experimental results demonstrate the effect of this coordinated HT attack, increasing the packet latency by 2.33x, increasing the link utilization by 1.74x and decreasing the instructions per cycle by 45 %, degrading N oC performance.