FPGA Based Hardware Accelerator for Training Implicit Neural Representations on Edge Devices

Training Deep neural networks using edge devices has been an active research problem being pursued rigorously with main focus on parameters like power, silicon area and time. This becomes more challenging when the non-linear activation functions are periodic in nature. This paper looks upon one such research problem of training Implicit Neural Representations (INRs) using FPGA based embedded platform. Training is performed by considering benchmark Rosenbrock function (also called Rosenbrock's valley or Banana Function). The proposed novel hardware architecture utilizes on-chip memory exclusively, for training the INR and was designed using AMD-Xilinx Vivado HLS 2019.2v and Vivado 2019.2v. The validation was performed using Xilinx PYNQ, with target being Avnet Ultra 96 v2 Embedded board that hosts AMD-Xilinx Zynq Ultrascale+MPSoC (XCZU3EG) FPGA device. The details about the resource utilization, power are provided. The acceleration that was achieved in comparison to Intel-CPU(i3-8100) (Jupyter Notebook with Tensorflow) - off shelf and no optimizations is 41x, thereby proving its sheer novelty for the considered benchmark.