Monolithic 3-D Integration of Diverse Memories: Resistive Switching (RRAM) and Gain Cell (GC) Memory Integrated on Si CMOS

The future memory is massive, diverse, and tightly integrated with computing. This research presents tight integration, both physically and architecturally, of two on-chip memory technologies, resistive switching random access memory (RRAM) and gain cell (GC) memory. HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub> RRAM and indium tin oxide (ITO) GC memory are monolithically integrated on 130-nm Si CMOS technology to form a joint memory that enables low-energy training and low-standby-power inference for edge devices. High-bandwidth on-chip data transfer can have a bandwidth that is 90× state-of-the-art (SoTA) HBM3E and 211× PCIe 7.0, enabled by high-density monolithic 3-D interconnections between memory arrays and high-speed transfer circuit within the integrated joint memory macro. Fabricated atomic layer deposition (ALD) ITO FET exhibits positive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>TH</roman></sub> of 0.67 V, excellent subthreshold slope (SS) of 65 mV/dec, high ON-current of 20 μA/μm, and low OFF-current of 5 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-<roman>18</roman></sup> A/μm, as extracted from >5000 s retention. The joint memory macro consumes 78% less standby power and 95% less training energy for MobileBERT compared to SRAM with iso-capacity. This RRAM-GC joint memory facilitates efficient continual learning in edge devices, addressing the challenges of a resource-constrained environment while supporting adaptive artificial intelligence (AI) model updates.