Impact of Back-Gate Bias on the Total Ionizing Dose and Hot Carrier Injection Effects in Double SOI nMOSFETs

Double silicon-on-insulator (DSOI) device exhibits high tolerance to total ionizing dose (TID) effect due to back gate bias (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>bg</roman></sub>) modulation. Negative <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>bg</roman></sub> is required to compensate for the performance degradation caused by the TID effect, while positive <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>bg</roman></sub> is required to compensate for the degradation caused by hot carrier injection (HCI) effect. This article focuses on the synergistic effect between TID and HCI under different back-gate voltage and modulation effect of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>bg</roman></sub>. The HCI effect is exacerbated by TID effect owing to the trapped charges in the oxide, which enhance the impact of ionizing in channel region. Δ<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> at 3 Mrad(Si) -<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> at 0 Mrad(Si) of DSOI MOSFET without stress is approximately -0.215 V, larger than that of stressed device. Additionally, applying a back-gate bias to mid-Si is an effective method to suppress the degradation in synergistic experiments.