A Novel Energy Efficient Single-Capacitor Switching Scheme for SAR ADCs

To alleviate the high energy consumption during the switching processing of capacitive digital to analog converter (CDAC) in successive approximation register analog-to-digital converters (SAR ADCs), this letter proposes a novel switching scheme. Based on the operation of voltage level shifting, decisions for the most significant bit (MSB) and the second MSB (2nd MSB) do not dissipate any energy. Subsequent decisions combine the advantages of monotonic and Vcm-based switching schemes, requiring only a single capacitor switch for each bit, simultaneously reducing the reference voltage shifting by half. The proposed switching scheme reduces capacitance distribution from “20C, …, 2N-1C” to “20C, …, 2N-3C,” which reduces the capacitance spread and thereby relaxes the capacitor matching requirements. Simulation results shows the reduction of switching energy consumption by 97.7%, and area saving by 75.0%. The proposed switching scheme is exploited in a prototype 10-bit, 20-KS/s SAR ADC. Measurements show an effective number of bits (ENOB) of 9.26 bits, a spurious-free dynamic range (SFDR) of 70.4 dB, and a power consumption of 45 nW, with CDAC energy at 10.8 nW.