Co-optimization of nanotube tunnel FET performance for implementation in low-power complementary ternary inverter

Abstract This article introduces the line tunneling-based gate-overlapped-source-only nanotube tunnel FET for the implementation of a low-power standard ternary inverter (STI). The proposed device exhibits a higher ON current with a steep subthreshold slope of 30 mV decade −1 while operating at V DD = 0.5 V. It is optimized for ternary operation, demonstrating gate-bias-independent point tunneling and gate-bias-dependent line tunneling. This device is meticulously optimized by varying the channel length, source doping, and drain doping, a process that is detailed in this article. The optimized device shows ∼96% improvement in static power dissipation, ∼50% improvement in dynamic power dissipation, and ∼49% improvement in the power-delay product compared to the conventional tunneling based ternary CMOS.