An Efficient Multi‐Core <scp>DSP</scp> Power Management Controller

ABSTRACT Today's society has entered a digital era, and the use of DSP is becoming increasingly frequent and important. In order to achieve the market targets of high energy efficiency, it is necessary to integrate low‐power design from the chip design stage. Based on FT‐xDSP chip architecture, this work designs a power management controller for DSP suitable for multi‐core and multi‐integrated peripherals from the perspective of power control in the chip design stage. This controller can precisely control the power supply, clock, and memory of each module in the DSP and introduces a clamp control unit in the power management controller to solve the problem of possible glitches during asynchronous reset and ensures that the system has no overflow of redundant requests. Additionally, a configurable state transition counter is also set up to avoid the problem of insufficient state transition time for low‐speed peripherals or long waiting time for high‐speed peripherals. After the pre‐tapeout experiment and post‐tapeout testing data analysis, the above new power control manager has excellent power management performance. In the low power consumption state of the chip, the overall power consumption of the core is reduced by over 95%, which is of great significance for achieving high‐efficiency processor chips.