A Design and Implementation of High-Efficiency Asymmetric Doherty Radio Frequency Power Amplifier for 5G Base Station Applications

Utilizing asymmetric Doherty technology, this paper designs a high-efficiency radio frequency (RF) power amplifier (PA) for 5G base station applications. To improve the performance of PA and narrow the gap between simulations and practices, we use compatibility methods to design the circuit, which keeps the layout dynamically adjustable. By incorporating redundant U-shaped microstrip lines, the impedance matching network can be dynamically fine-tuned during debugging based on real-time hardware conditions. Furthermore, independent debugging paths for both main and auxiliary amplifiers are designed to enable the multi-stage debugging strategy. Performing separate debugging for each branch first, followed by combined debugging ensures both amplifiers achieve optimal operation states. The proposed strategy improves debugging efficiency while achieving precise parameter optimization. To verify the feasibility of the scheme proposed in this paper, we use CGHV40030F transistors to design a Doherty PA worked at 3.5 GHz and complete the hardware implementation and tests. Simulations and practice results prove that the architecture of asymmetric Doherty increases the back-off efficiency, and the compatibility design can make debugging easy and align the practice results closely with the simulations. We observe the saturation drain efficiency of 73.5% and the back-off efficiency of 47.5% from measurements, which confirms the effectiveness of the proposed compatibility design approach.