Design and circuit applications of PTnMOSFET devices from planar to gate-all-around structures

In this work, we propose a punch-through nMOSFET (PTnMOSFET) as a practical alternative to pMOSFETs by adjusting the source/drain doping concentrations. This PTnMOSFET design simplifies device fabrication by eliminating the need for sizing adjustments or stress engineering techniques while effectively addressing current mismatch issues between pMOSFETs and nMOSFETs. Simulations of Planar, Fin Field-Effect Transistor (FinFET), and Gate-All-Around (GAA) PTnMOSFETs reveal that the GAA PTnMOSFET achieves a wide design window, an average subthreshold swing (SSavg) of 74 mV/dec, and an ION(PTnMOSFET)/ION(nMOSFET) ratio of 0.89. Gate lengths (LG) of 30 nm and 14 nm were selected to align with current and emerging semiconductor technology nodes, ensuring relevance to state-of-the-art devices. In circuit applications, the GAA single-carrier (SC) circuit exhibits significant improvements over the conventional (Conv.) GAA circuit (with Wp/Wn = 1). The GAA SC circuit demonstrates a 14.9% shorter delay time, a 5.5% higher voltage gain, and more symmetric signal noise margins (NM), with 117 mV for signal noise margin high (NMH) and 118 mV for signal noise margin low (NML). Benchmarking results further suggest that under the same supply voltage (VDD) and number of transistors, our GAA SC Static Random Access Memory (SRAM) achieves a read failure voltage of 0.145 V and a static signal noise margin of 56 mV in read mode, surpassing state-of-the-art studies on stacked nanosheet and cFET counterparts. While these results highlight the strengths of the proposed design, further experimental validation under diverse operating conditions is essential to fully assess its robustness and practical applicability.