Low Power Two Stage CMOS Operational Amplifier

Abstract: Operational amplifier (Op-Amp) circuits play a critical role in computation, instrumentation, and a variety of industrial applications. With the growing demand for precision Op-Amps in automotive and industrial environments, there is an increasing need for designs that offer enhanced accuracy and robust performance across wide temperature ranges. The shift towards integrating both analog and digital circuits on a single chip has made Complementary Metal-Oxide Semiconductor (CMOS) technology the preferred choice over traditional bipolar technologies for analog circuit design in mixed-signal systems. Among various Op-Amp topologies, the two-stage architecture remains one of the most widely adopted due to its favorable gain and output swing characteristics. This paper presents the design and simulation of a CMOS-based two-stage fully differential operational amplifier, optimized for low-power and low-voltage operation. The amplifier is biased with a current of 20 µA and is implemented using both 180 nm and 90 nm CMOS process technologies. Special emphasis is placed on operation in the sub-threshold region, where the unique behavior of MOS transistors facilitates ultra-low-voltage and low-current operation. The proposed Op-Amp is intended for on-chip applications with capacitive load requirements in the picofarad range. Simulation results are obtained using the Cadence Virtuoso design environment and demonstrate the performance of the amplifier across key parameters in both technology nodes