A 0.92-pJ/b 112-Gb/s PAM-4 Transmitter With Bandwidth and Linearity Enhanced Quasi-Voltage-Mode Driver and Reconfigurable Three-Tap T/2–T Variable Fractional-Spaced FFE in 28-nm CMOS

This study presents a 112-Gb/s four-level pulse-amplitude modulation transmitter implemented in a 28-nm CMOS process. An innovative quasi-voltage-mode driver is proposed, which demonstrates similar bandwidth compared to the current-mode logic driver with an approximately 30% power reduction and provides flexible linearity fine-tuning. The TX architectures with and without the pre-driver stage are optimized to exploit the bandwidth limit further. A three-tap T/2–T variable-spaced feed-forward equalizer is designed to realize reconfigurable 0.5-T, 0.6-T, 0.75-T, and 1-T tap delays, which enables customized eye-opening optimization under different data rates and channel responses. The measurement results show that the energy efficiency of the proposed TX is 0.92 pJ/b with a 0.9-Vppd DC output swing, and the best level separation mismatch ratios are 99.8% and 99.6% at 100-Gb/s and 112-Gb/s, respectively.