Designing Low-Loss Single-Inductor Multiple-I/O (SL-MI/O) CMOS Power Supplies

Switched-inductor power supplies are valued for their high efficiency despite the bulkiness of off-chip inductors. When designing compact systems like portable consumer electronics and wireless microsensors, single-inductor topologies are therefore preferred. Specifically, single-inductor multi-input and multi-output (SL–MI/O) power supply designs pose unique challenges that have yet to be fully addressed. This paper aims to provide design guidelines for maximizing efficiency in the design of SL–MI/O systems, especially in the sub-5W domain. To simplify the choice between NFETs and PFETs for the multitude of power switches in SL–MI/Os, which is not straightforward, an intuitive metric called the Favorability Index (F<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>NP</roman></sub>) is proposed. A new, optimal supply voltage theory is also presented, suggesting that the most efficient voltage to supply power switches’ gates is around twice the threshold voltage (v<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>T</roman></sub>). The paper also proposes using dynamic selectors in gate drivers. This allows for blocking cross conduction without increasing v<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>SUP</roman></sub> drastically, ensuring efficiency. A two-transistor selector is recommended as a simple implementation, and the tradeoffs are discussed. An example topology is designed using guidelines proposed by the paper to demonstrate the design flow and efficiency improvements.