Elucidating the Role of Ferroelectric in Memory Window Expansion of Ferroelectric FETs With Gate-Side Injection

In this work, we present a comprehensive experimental and modeling study to clarify the role of the ferroelectric (FE) layer in enhancing the memory window (MW) of FeFETs with gate-side charge injection. We separated the FE contributions to the MW into remnant polarization and top charge trap layer (CTL) trapping. Our findings demonstrate that: 1) FE layer expands the MW in two ways: by enhanced FE polarization induced by gate-side charge trapping into the CTL and through their superlinear <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i>FE–<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i>FE relationship that boosts the CTL electric field and enhances charge trapping; 2) the contributions from polarization and CTL trapping mutually reinforce each other, resulting in a larger MW compared to a FE + dielectric stack or a high-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> + CTL stack, where, in both stacks, only one factor is active; 3) enhanced polarization strengthens the channel interfacial layer electric field, suppressing electron detrapping from the channel and, thus, enabling immediate read–after–write, thereby improving FeFET read throughput; and 4) the MW can be further increased incorporating a blocking oxide layer above the CTL, achieving a 12-V window with a 2-nm-thick Al2O3 layer.