MRAM-Based Cache and In-Memory Computing

The rapid advancement in semiconductor technology has led to a significant gap between the processing capabilities of CPUs and the access speeds of memory, presenting a formidable challenge known as the “memory wall” in traditional Von Neumannarchitectures. Concurrently, the “power wall” dilemma emerges, characterized by escalated transmission overhead due to rapid data transfer and increased static power consumption from the downsizing of CMOS transistors. Addressing these issues, recent research has centered on more energy-efficient design and utilization of caches, thus giving rise to: first, emerging cache designs introducing ultra-low power non-volatile memory (NVM) techniques, and in-memory computing exploiting direct computation from NVM caches. Among the various non-volatile memory technologies, Magnetic Random Access Memory (MRAM) has emerged as one of the most promising technology owing to its high density/performance, low power consumption, and near-infinite lifetime. Hence, in this paper methodically examines MRAM’s distinct models and array configurations, reviews optimization techniques for its peripheral circuits, and evaluates MRAM-based cache architectures. At the same time, it highlights the latest MRAM-IMC prototypes and their progressive applications.