Broadband Characterization of Interconnects in Die-Embedded Glass Interposer

This article presents a broadband <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i>-parameter characterization of embedded and vertical transitions between chips embedded in a glass interposer. We discuss the opportunities that die-embedded glass interposer presents for heterogeneous integration by enabling vertical and lateral die-to-die interconnects with increased bandwidth and reduced length, as well as low-loss chip-to-interposer interconnects between RF chips and passives. Multiple back-to-back (B2B) chain structures with different lengths are designed on a high-resistivity silicon test die, which is embedded in the glass interposer with two redistribution layers (RDLs) with stacked microvias. The electrical characterization includes obtaining two-port <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i>-parameters (dc–170 GHz) of the stacked microvia interconnect by applying a two-step TRL de-embedding procedure to remove the chip-level and interposer-level transmission lines. Crosstalk measurements are also presented up to 50 GHz. Crosstalk for all chain structures is better than −30 dB at the near end and −25 dB at the far end. The measured <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i>-parameters of the interconnect show 0.2-dB insertion loss at 170 GHz. This represents the first broadband characterization results for chips embedded in the glass interposer.