Development of the Front-End Readout Electronics prototype for the HFRS-TPC detector

Abstract A 256-channel readout electronics prototype system for TPC detector on High Energy FRagment Separator (HFRS) was proposed and implemented. The system consists of eight ASIC Boards, four Front-End Electronics (FEE) boards and a Data Concentrate Unit (DCU). The ASIC board based on ASICs composed of preamplifiers and shapers. Then the FEE digitizes waveforms and extracts the time and energy information with linear interpolation algorithm and peak searching algorithm. The DCU aggregates data from multiple FEEs and transfers to the computer via PCIe interface. In the dynamic range of input charge from 10 fC to 900 fC, the output amplitude nonlinearity of the prototype system is better than 1.5%. The energy resolution is better than 3%. The test results with TPC illustrate that with a laser source tests a position resolution is better than 330 μm.