Design of Digital Phase Frequency Detector in ADPLL RF Transceiver

CMOS technology advancements have significantly enhanced smart farming monitoring system (SFMS) miniaturization and efficiency, especially in transceivers using All-Digital Phase-Locked Loops (ADPLLs). The ADPLL's phase-frequency detector (PFD) evaluates two digital inputs to identify frequency and phase errors. A time-to-digital converter (TDC), typically used by the PFD block, has high power usage and slow phase-frequency acquisition. Therefore, the study aims to minimize the high-power consumption and improve the fast phase-frequency acquisition of traditional Phase-Frequency Detectors (PFDs) by developing a Verilog HDL-optimized digital PFD explicitly designed for ultra-low power ADPLLs. The simulation results revealed a duty cycle of 34.2%, no frequency difference, and a time difference of 0.05 ns, suggesting accurate phase error detection and correction. The PFD's fast response time and minimal dead zone impact assure fast phase lock, which is crucial for SFMS in real-time. Furthermore, the ultra-low power and fast locking range required by the Verilog-simulated PFD design make it ideal for SFMS applications. This research highlights how improved PFD designs may develop high-performance, low-power ADPLL transceivers.