Extremely High ESD Failure Voltage of RESURF LDMOS Devices for ESD Resilient Driver Applications
This work reports an extremely high ESD failure voltage in the transmission line pulse (TLP) characteristics of the laterally diffused metal-oxide-semiconductor (LDMOS) devices, while investigating a correlation between the critical voltage and filament formation. A high failure voltage enables an additional immunity to ESD damage by providing extra protection against the overvoltage stress in high-voltage (HV) I/O applications. The ESD behavior of LDMOS devices in the presence of reduced surface field (RESURF)-implant in the drift region is investigated in detail. Furthermore, an approach to drift region design and electric field engineering that affects this high failure voltage in RESURF LDMOS devices is discussed, using measurement and 3-D TCAD simulation.
Authors
- M. Monishmurali
- Aakanksha Mishra (ORCID: https://orcid.org/0000-0001-5059-8504)
- Mayank Shrivastava (ORCID: https://orcid.org/0000-0003-1005-040X)
- Shaik Ahamed Suzaad
- Ankur Gupta (ORCID: https://orcid.org/0000-0003-2179-3612)
- Amit Kumar Singh (ORCID: https://orcid.org/0000-0003-2088-1450)
- Avinash Kumar Singh (ORCID: https://orcid.org/0000-0002-5755-0252)
- Shubham Kumar (ORCID: https://orcid.org/0000-0002-0590-686X)
- B. Sampath Kumar (ORCID: https://orcid.org/0000-0002-5055-9529)
- Kiran Pote Sanjay
Institutions
- Indian Institute of Science Bangalore (IN)
- Indian Institute of Technology Delhi (IN)
Publication Details
- Journal
- IEEE Transactions on Electron Devices
- Published
- 2025-04-09
- DOI
- https://doi.org/10.1109/ted.2025.3556114
- Citations
- 1
- Primary Topic
- Electrostatic Discharge in Electronics
- Type
- article
- Field-Weighted Citation Impact
- 0.73