Accelerating Fault Injection for Validating Processor RTL Implementations

With the increasing probability of software errors being caused by hardware transient faults, hardware engineers require better methods to evaluate the impact of faults and determine how to harden their products against them. This paper presents novel techniques to accurately and efficiently simulate faults on processors by dynamically switching, with little designer effort, a simulation from RTL-level-or-lower to instruction-level. When combined with known techniques, the proposed techniques make fault modeling orders-of-magnitude faster than RTL simulation while achieving the same level of accuracy, enabling fast identification of the portions of the design that would benefit most from hardening, and providing statistical guarantees of a design's resistance to faults.