An Effective Analytical Placement Approach to Handle Fence Region Constraint

Fence region constraints are essential in cell placement, as they can enhance design convergence speed and improve placement quality. This paper introduces a multilevel framework approach to tackle this challenge while maintaining placement quality and reducing complexity. First, the coarsening stage utilizes a fence region aware clustering to avoid inappropriate groupings. Next, recursive quadratic programming is employed to achieve a better initial cell distribution. Previous methods may result in longer wire-length because they typically assign fence objects to their placement regions before distributing cells over a placement region. To mitigate wirelength increases caused by overly restrictive constraints, our refinement stage uses a three-phase approach to gradually adjust the placement regions of fence objects. Additionally, cells are distributed across desired regions using an analytical placement formulation that includes a fence region aware penalty term. Experimental results demonstrate that our methodology achieves improved wirelength and routability while effectively managing fence region constraints.

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Publication Details

Published
2024-10-27
DOI
https://doi.org/10.1145/3676536.3676688
Citations
2
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
0.42

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article

An Effective Analytical Placement Approach to Handle Fence Region Constraint

Yung-Chen Chen, Che-Li Lin, De-Shiun Fu, Chen-Fa Tsai et al.
2 citations
VLSI and FPGA Design Techniques
0.42
article

An Effective Analytical Placement Approach to Handle Fence Region Constraint

Yung-Chen Chen, Che-Li Lin, De-Shiun Fu, Chen-Fa Tsai, Jai-Ming Lin, Wei-Yuan Lin, P.H. Chen
article en
2 citations

Abstract

Fence region constraints are essential in cell placement, as they can enhance design convergence speed and improve placement quality. This paper introduces a multilevel framework approach to tackle this challenge while maintaining placement quality and reducing complexity. First, the coarsening stage utilizes a fence region aware clustering to avoid inappropriate groupings. Next, recursive quadratic programming is employed to achieve a better initial cell distribution. Previous methods may result in longer wire-length because they typically assign fence objects to their placement regions before distributing cells over a placement region. To mitigate wirelength increases caused by overly restrictive constraints, our refinement stage uses a three-phase approach to gradually adjust the placement regions of fence objects. Additionally, cells are distributed across desired regions using an analytical placement formulation that includes a fence region aware penalty term. Experimental results demonstrate that our methodology achieves improved wirelength and routability while effectively managing fence region constraints.

Global Unichip (Taiwan) (TW), National Cheng Kung University (TW)
Ministry of Science and Technology, Taiwan
Climate action
Openalex Percentile: Top 35%
VLSI and FPGA Design Techniques
0.42
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