2024 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-Flop

In modern designs, timing performance, power, and area constraints (PPA) are the three major metrics for physical design. 2024 ICCAD CAD Contest Problem B investigates the optimization of power, area, and timing in modern semiconductor designs through the strategic use of multibit flip-flops. By banking flip-flops, more area can be freed up, and also efficiently reduce power consumption and reduce net routing complexity. While multibit flip-flop banking has been effective in reducing power and area, it could negatively impact timing performance in critical paths, thus multibit flip-flop debanking could be performed to alleviate timing critical paths. 2024 ICCAD CAD Contest Problem B presents a challenge where participants must optimize the virtual designs by dynamically applying banking and debanking techniques to achieve optimized trade-offs among PPA.