Low‐Thermal‐Budget Construction of Carbon Nanotube p‐FET on Silicon n‐FET toward 3D CMOS FET Circuits with High Noise Margins and Ultra‐Low Power Consumption

Abstract 3D integration presents a potential technical solution to break the fundamental transistor density limit of the ground rule scaling. Despite notable progress, the unavoidable high thermal budget in conventional silicon‐transistor‐based 3D integration results in high process complexity and degraded device performances. Herein, a heterogeneous 3D complementary metal‐oxide‐semiconductor field effect transistor (CMOS FET) technology, integrating carbon nanotube (CNT) transistors into Si back‐end‐of‐line (BEOL) processes is presented. Experiments show that CNT transistors can be integrated using a low‐thermal‐budget (<150 °C) process, requesting little modification in the well‐established Si processes. Comparative analysis also indicates that the low‐thermal‐budget integration results in little damage to the Si components. More importantly, Si‐BEOL‐compatible gate control enhancement and threshold voltage modulation techniques for CNT transistors are developed, resulting in noise margin improvement and power suppression in inverters. The experimental results further demonstrate that CMOS FET inverters feature high noise margins ( NM H / NM L = 0.404/0.353 × V DD ) and ultra‐low power consumption (390 pW, >100× lower than those in the Si counterparts). Moreover, numerical simulations predict that 14‐nm‐node CNT/FinFET 3D CMOS FET inverters outperform the conventional FinFET counterparts in noise margins and power efficiency. These findings demonstrate the possibility of 3D integration's complexity reduction by adopting <150 °C CNT‐based processes.