An optimized implementation of adaptive noise canceller based on proposed shift and add multiplier

Information is deteriorated by communication channels in several ways. The most notable is the addition of noise to the signal during transmission. Noise is reduced by the use of adaptive filters. Wiener, Steepest, and LMS are the most often utilized. While in hardware translation on ASICS and FPGAs, adaptive filters require more resources than straightforward FIR or IIR designs. Reducing resources is necessary to optimize the implementation. The literature on resource-optimized filter implementation with multiplier optimization has been seen with a number of approaches. In this study, a new proposed shift and add multiplier is used to create an FPGA-based adaptive noise canceller based on the Steepest -descent algorithm, and its performance is compared with a traditional version. The adaptive noise canceller is first simulated in MATLAB and then designed in Xilinx Virtex 7 FPGA using the ISE 14.7 tool, but the proposed architecture is too flexible to be carried out on any FPGA board. The suggested shift and add multiplier consume less FPGA resources than the original shift and add multiplication scheme alone, and in designing an adaptive noise canceller. The proposed method also performs better than the conventional approach in terms of maximum frequency achieved. Therefore, it can be inferred that the proposed shift and add multiplier approach can be adapted for resource-optimized implementation in the communication domain and in DSP applications.