SeGen: Automatic Topology Generator for Sequencing Elements

Sequencing elements, such as flip-flops (FFs), significantly impact the speed, size, and power consumption of digital integrated circuits. Despite numerous sequencing-element proposals in the past, they have heavily relied on the expertise of designers, and their design method could not search all available FF topologies. This paper introduces a design framework for automatically generating sequencing element designs, named SeGen. Motivated by the fact that the operation of all digital circuits can be represented by a Boolean function, we present SeGen which initially generates all possible Boolean functions for sequencing elements and derives circuit topologies from each of them. By adjusting the functionality qualification step of Boolean functions, SeGen can generate other sequencing elements such as toggle FFs and dual-edge-triggered FFs as well. A total of 40 resulting topologies newly generated by SeGen encompass the entire spectrum of positive-edge-triggered FFs, including master-slave FFs and pulsed latches, and consequentially provide a range of designs suitable for diverse applications. Several generated FFs such as SeGen8 and SeGen28 outperform recent human-crafted FFs and exhibit energy-delay product (EDP) improvement of 203%--257% at 1V supply voltage, compared to conventional transmission-gate FF (TGFF).