GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs

The Rectilinear Steiner Minimum Tree (RSMT) problem is a fundamental problem in VLSI placement and routing and is known to be NP-hard. Traditional RSMT algorithms spend a significant amount of time on finding Steiner points to reduce the total wire length or use heuristics to approximate producing sub-optimal results. We show that Graph Neural Networks (GNNs) can be used to predict optimal Steiner points in RSMTs with high accuracy and can be parallelized on GPUs. In this paper, we propose GAT-Steiner, a graph attention network model that correctly predicts 99.846% of the nets in the ISPD19 benchmark with an average increase in wire length of only 0.480% on suboptimal wire length nets. On randomly generated benchmarks, GAT-Steiner correctly predicts 99.942% with an average increase in wire length of only 0.420% on suboptimal wire length nets.

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Publication Details

Published
2024-10-27
DOI
https://doi.org/10.1145/3676536.3676683
Citations
3
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
0.63
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article

GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs

Muhammad Hadir Khan, Bugra Önal, Matthew R. Guthaus, Eren Dogan
3 citations
VLSI and FPGA Design Techniques
0.63
article

GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs

Muhammad Hadir Khan, Bugra Önal, Matthew R. Guthaus, Eren Dogan
article en
3 citations

Abstract

The Rectilinear Steiner Minimum Tree (RSMT) problem is a fundamental problem in VLSI placement and routing and is known to be NP-hard. Traditional RSMT algorithms spend a significant amount of time on finding Steiner points to reduce the total wire length or use heuristics to approximate producing sub-optimal results. We show that Graph Neural Networks (GNNs) can be used to predict optimal Steiner points in RSMTs with high accuracy and can be parallelized on GPUs. In this paper, we propose GAT-Steiner, a graph attention network model that correctly predicts 99.846% of the nets in the ISPD19 benchmark with an average increase in wire length of only 0.480% on suboptimal wire length nets. On randomly generated benchmarks, GAT-Steiner correctly predicts 99.942% with an average increase in wire length of only 0.420% on suboptimal wire length nets.

University of California, Santa Cruz (US)
Zero hunger
Openalex Percentile: Top 30%
VLSI and FPGA Design Techniques
0.63
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