TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation

In a compilation flow of processor-based emulation (PBE), partitioning involves dividing a large netlist into smaller pieces and assigning them to different processors. Furthermore, the scheduling process must adhere to the levels of the netlist, which are determined by topological ordering, and the logic gates in the same level can be emulated in parallel. However, during the netlist partitioning stage, assigning most gates at the same level to one processor would undermine the benefits of parallelization in scheduling, leading to overall performance degradation. This paper proposes the TopoOrderPart, the first scheduling-driven partitioning framework for simultaneous balancing topological order and minimizing the cut size, which holds significant value in reducing time steps of scheduling. In particular, the topological order balancing and cut size are considered throughout the multilevel paradigm, and balance-aware coarsening achieves balancing between clusters in the early stage, with super-far root growing initial partitioning obtaining the better partition by selecting those root nodes in distant relationship within the connection space and two novel TopoRefine algorithms further enhancing the solution. Experimental results show TopoOrderPart can improve 69% topological order balancing and 0.53× run time while maintaining comparable cut size, compared to the state-of-the-art partitioner.

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Published
2024-10-27
DOI
https://doi.org/10.1145/3676536.3676833
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
0.00

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article

TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation

Shunyang Bi, Hailong You, Hongbing Wu, Cong Li et al.
Embedded Systems Design Techniques
article

TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation

Shunyang Bi, Hailong You, Hongbing Wu, Cong Li, Richard Sun, Jing Tang
article en

Abstract

In a compilation flow of processor-based emulation (PBE), partitioning involves dividing a large netlist into smaller pieces and assigning them to different processors. Furthermore, the scheduling process must adhere to the levels of the netlist, which are determined by topological ordering, and the logic gates in the same level can be emulated in parallel. However, during the netlist partitioning stage, assigning most gates at the same level to one processor would undermine the benefits of parallelization in scheduling, leading to overall performance degradation. This paper proposes the TopoOrderPart, the first scheduling-driven partitioning framework for simultaneous balancing topological order and minimizing the cut size, which holds significant value in reducing time steps of scheduling. In particular, the topological order balancing and cut size are considered throughout the multilevel paradigm, and balance-aware coarsening achieves balancing between clusters in the early stage, with super-far root growing initial partitioning obtaining the better partition by selecting those root nodes in distant relationship within the connection space and two novel TopoRefine algorithms further enhancing the solution. Experimental results show TopoOrderPart can improve 69% topological order balancing and 0.53× run time while maintaining comparable cut size, compared to the state-of-the-art partitioner.

Xidian University (CN)
National Natural Science Foundation of China, Higher Education Discipline Innovation Project
Openalex Percentile: Top 67%
Embedded Systems Design Techniques
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TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation — Shunyang Bi, Hailong You, et al. · (2024) | TGRS Research Map | TGRS