Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration

Placement is a crucial step in the physical synthesis flow that significantly determines the timing performance of a design. In this paper, we propose a timing-driven global placement framework with a hybrid pin-based weighting scheme that considers both graph and path information and an optimization-friendly RC tree and wirelength model. A calibration method is proposed to further improve the incremental timing. Experiment results show over 37% improvement on TNS and 15% improvement on WNS, with 4.2% less HPWL on the ICCAD 2015 benchmark compared to the state-of-the-art GPU-accelerated differentiable timing-driven placer, while also being around 2x faster.

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Publication Details

Published
2024-10-27
DOI
https://doi.org/10.1145/3676536.3676803
Citations
6
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
1.25
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article

Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration

Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young, Lixin Liu
6 citations
VLSI and FPGA Design Techniques
1.25
article

Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration

Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young, Lixin Liu
article en
6 citations

Abstract

Placement is a crucial step in the physical synthesis flow that significantly determines the timing performance of a design. In this paper, we propose a timing-driven global placement framework with a hybrid pin-based weighting scheme that considers both graph and path information and an optimization-friendly RC tree and wirelength model. A calibration method is proposed to further improve the incremental timing. Experiment results show over 37% improvement on TNS and 15% improvement on WNS, with 4.2% less HPWL on the ICCAD 2015 benchmark compared to the state-of-the-art GPU-accelerated differentiable timing-driven placer, while also being around 2x faster.

Chinese University of Hong Kong (HK)
Affordable and clean energy
Openalex Percentile: Top 19%
VLSI and FPGA Design Techniques
1.25
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