Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration
Placement is a crucial step in the physical synthesis flow that significantly determines the timing performance of a design. In this paper, we propose a timing-driven global placement framework with a hybrid pin-based weighting scheme that considers both graph and path information and an optimization-friendly RC tree and wirelength model. A calibration method is proposed to further improve the incremental timing. Experiment results show over 37% improvement on TNS and 15% improvement on WNS, with 4.2% less HPWL on the ICCAD 2015 benchmark compared to the state-of-the-art GPU-accelerated differentiable timing-driven placer, while also being around 2x faster.
Authors
- Bangqi Fu (ORCID: https://orcid.org/0000-0003-2216-2855)
- Martin D. F. Wong (ORCID: https://orcid.org/0000-0001-8274-9688)
- Evangeline F. Y. Young (ORCID: https://orcid.org/0000-0003-0623-1590)
- Lixin Liu (ORCID: https://orcid.org/0000-0002-8451-8100)
Institutions
- Chinese University of Hong Kong (HK)
Publication Details
- Published
- 2024-10-27
- DOI
- https://doi.org/10.1145/3676536.3676803
- Citations
- 6
- Primary Topic
- VLSI and FPGA Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 1.25