EasyPart: An Effective and Comprehensive Hypergraph Partitioner for FPGA-based Emulation

Logic verification becomes more and more important for the design of large-scale digital integrated circuits (ICs). This makes FPGA-based hardware emulation an imperative step in the design flow, and how to effectively partition and map the circuit netlist into the multi-FPGA system (MFS) for emulation is of concern. In this paper, we present EasyPart, an effective and comprehensive hypergraph partitioner for the FPGA-based hardware emulation. EasyPart can handle the practical constraints in the MFS for logic emulation and includes novel techniques for pursuing minimum hop during topology-driven partitioning and treating the interconnection constraints. We have evaluated EasyPart against state-of-the-art partitioners on public benchmarks. The results show that EasyPart can reduce the cutsize with a comparable or shorter runtime. EasyPart is capable of finding non-hop solutions with better robustness and performance compared to previous work. It also achieves significant improvements in terms of time division multiplexing (TDM) ratio and maximum hop when tested on industrial cases.