Error Correction and Detection for Analog AI Computing in Edge Systems

To realize the full potential of deep neural networks (DNNs) in AI-empowered edge systems, DNNs need to be much more efficient. Analog in-memory computing can potentially improve the speed and energy efficiency of AI by multiple orders, and break the "memory wall" that is currently a major bottleneck for AI. This work explores the design of analog error-correcting codes (Analog ECCs). The codes focus on the correction of errors in vector-matrix multiplications, which are a dominant part of computation in DNNs. The codes consider small but ubiquitous noise in analog edge circuits as tolerable, and focus on the correction of large errors. It presents a linear-programming based algorithm that finds the error correction/detection capabilities of codes. It also presents a number of newly discovered codes that achieve state-of-the-art performance.