A Co-optimization Framework with Multi-layer Constraints for Manufacturability

Adherence to design rule constraints, a cornerstone principle of Design for Manufacturability (DFM), is essential for ensuring successful fabrication in modern circuit design. As the foundries keep introducing more customization for better performance, new design rule challenges emerge with the device layers, such as implant layer constraints in the designs with multiple threshold voltages, and the trim poly layer constraints in the self-aligned double patterning (SADP). These constraints are typically tackled in the legalization stage. In addition, during the chip finishing, fillers are inserted for better manufacturability, such as a more uniform chip surface and a more robust power integrity. However, improper filler insertion might undermine the previous legalized layout. This paper presents a co-optimization framework in the legalization and filler insertion stage, which is extensible for other layer constraints. We model the filler insertion problem as a multi-branch tree and present a dynamic programming-based pre-pruning algorithm, which is also able to detect violations in the legalization stage. To reduce runtime, we additionally propose two violation detectors for legalization based on the look-up table (LUT) inference and greedy algorithm. Experimental results show that our filler insertion algorithm can significantly reduce the number of violations compared with state-of-the-art work. With our violation detectors in legalization, the co-optimization framework achieves better performance compared with the commercial tool.