FLOP: A Flexible Memory-Optimized Processor for Parallel Graph Mining on FPGA

Graph mining is an important and complex emerging algorithmic model with extensive applications in fields including social sciences, chemoinformatics, and bioinformatics. However, contemporary graph mining accelerators still face challenges related to excessive on-chip resource utilization, and low set processing efficiency. To address these issues, we propose FLOP, a memory-optimized processor that leverages a new on-chip and off-chip memory partitioning design scheme. First, FLOP's memory design can accommodate the varying memory requirements of graph vertex sets. Second, we devise input-size aware processing engines (PEs) to optimize resource utilization and maximize computation efficiency. Third, FLOP adopts a pattern-aware instruction set architecture and a two-stage compiler to satisfy the mining needs of different patterns. We evaluated FLOP using five commonly used datasets and different pattern mining tasks. Experiment results show that, FLOP outperforms the state-of-the-art FPGA-based accelerator Gramer by 3.09× ~ 15.93× and compared to the CPU-based design GraphPi, FLOP achieves an average of 6.55× speedup. Additionally, FLOP also has competitive performance compared to the ASIC-based design FINGERS.