MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management

Modern ASIC placement tools encompass three categories of region constraints: default regions, fence regions, and guide regions. Region constraints pose significant challenges to existing placement algorithms, compromising the versatility and robustness required for diverse placement workloads. In this work, we propose MORPH, a more robust ASIC placer designed for hybrid region constraints. We integrate hybrid region constraints into a unified multi-electrostatic formulation that features a shared electrostatics model and a binary-lifting-based region pruning algorithm. We develop a more robust nonlinear placement framework that includes second-order information and a hybrid-region-aware legalization algorithm to address convergence issues. Experiments on the ISPD 2015 benchmark suite demonstrate 5.6-14.3% HPWL improvement and 10--24% overflow reduction compared to state-of-the-art region-aware placers. Further experiments on the ISPD 2015 benchmark suite and its variants show that the proposed techniques can achieve over 30% HPWL improvement and up to a twofold reduction in overflow with more stable convergence.

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Publication Details

Published
2024-10-27
DOI
https://doi.org/10.1145/3676536.3676745
Citations
2
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
0.42

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article

MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management

Yibo Lin, Runsheng Wang, Jing Mai, Zuodong Zhang et al.
2 citations
VLSI and FPGA Design Techniques
0.42
article

MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management

Yibo Lin, Runsheng Wang, Jing Mai, Zuodong Zhang, Ru Huang
article en
2 citations

Abstract

Modern ASIC placement tools encompass three categories of region constraints: default regions, fence regions, and guide regions. Region constraints pose significant challenges to existing placement algorithms, compromising the versatility and robustness required for diverse placement workloads. In this work, we propose MORPH, a more robust ASIC placer designed for hybrid region constraints. We integrate hybrid region constraints into a unified multi-electrostatic formulation that features a shared electrostatics model and a binary-lifting-based region pruning algorithm. We develop a more robust nonlinear placement framework that includes second-order information and a hybrid-region-aware legalization algorithm to address convergence issues. Experiments on the ISPD 2015 benchmark suite demonstrate 5.6-14.3% HPWL improvement and 10--24% overflow reduction compared to state-of-the-art region-aware placers. Further experiments on the ISPD 2015 benchmark suite and its variants show that the proposed techniques can achieve over 30% HPWL improvement and up to a twofold reduction in overflow with more stable convergence.

Peking University (CN)
National Science Foundation, National Natural Science Foundation of China, Higher Education Discipline Innovation Project
Openalex Percentile: Top 35%
VLSI and FPGA Design Techniques
0.42
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