One-for-All: An Unified Learning-based Framework for Efficient Cross-Corner Timing Signoff

In advanced technology nodes, the proliferation of process corners poses significant challenges in timing signoff, particularly in estimating wire-induced interconnect delay across process corners. This paper proposes a learning-based framework to perform cross-corner timing prediction efficiently and accurately. It seamlessly integrates learning-based reference corner selection and topology-aware interconnect timing prediction into the broader timing signoff steps and Engineering Change Order (ECO) processes. Unlike previous methods, it only requires information about one single known corner while accurately predicting all unknown corners. Evaluated on two mainstream industry processes, the proposed framework surpasses alternative machine learning models and existing strategies, with an impressive average accuracy enhancement of 62.6% and 95.3% respectively, and maintains a low mean absolute error (MAE) under 0.37ps and 0.01ps. Additionally, a faster version of the framework is developed to predict interconnect delay directly from a single extracted SPEF, yielding over 2× speedup. Moreover, the single-corner approach featured by the framework significantly accelerates ECO processes by over 10× compared to standard timing signoff flows. The proposed framework is also set to be open-sourced at a later date.

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Publication Details

Published
2024-10-27
DOI
https://doi.org/10.1145/3676536.3676656
Citations
1
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
0.21

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article

One-for-All: An Unified Learning-based Framework for Efficient Cross-Corner Timing Signoff

Xinfei Guo, Libo Zhu, Yichen Cai
1 citations
Low-power high-performance VLSI design
0.21
article

One-for-All: An Unified Learning-based Framework for Efficient Cross-Corner Timing Signoff

Xinfei Guo, Libo Zhu, Yichen Cai
article en
1 citations

Abstract

In advanced technology nodes, the proliferation of process corners poses significant challenges in timing signoff, particularly in estimating wire-induced interconnect delay across process corners. This paper proposes a learning-based framework to perform cross-corner timing prediction efficiently and accurately. It seamlessly integrates learning-based reference corner selection and topology-aware interconnect timing prediction into the broader timing signoff steps and Engineering Change Order (ECO) processes. Unlike previous methods, it only requires information about one single known corner while accurately predicting all unknown corners. Evaluated on two mainstream industry processes, the proposed framework surpasses alternative machine learning models and existing strategies, with an impressive average accuracy enhancement of 62.6% and 95.3% respectively, and maintains a low mean absolute error (MAE) under 0.37ps and 0.01ps. Additionally, a faster version of the framework is developed to predict interconnect delay directly from a single extracted SPEF, yielding over 2× speedup. Moreover, the single-corner approach featured by the framework significantly accelerates ECO processes by over 10× compared to standard timing signoff flows. The proposed framework is also set to be open-sourced at a later date.

Shanghai Jiao Tong University (CN)
Shanghai Jiao Tong University, National Science and Technology Major Project
Openalex Percentile: Top 43%
Low-power high-performance VLSI design
0.21
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